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cystech electronics corp. spec. no. : c744v8 issued date : 2014.11.03 revised date : page no. : 1/13 MTBA5C10V8 cystek product specification n- and p-channel logic level enhancement mode mosfet MTBA5C10V8 features ? simple drive requirement ? low on-resistance ? fast switching speed ? pb-free lead plating and halogen-free package equivalent circuit outline ordering information device package shipping MTBA5C10V8-0-t6-g dfn3 3 (pb-free lead plating and halogen-free package) 3000 pcs / tape & reel MTBA5C10V8 dfn3 3 g gate s source d drain n-ch p-ch bv dss 100v -100v i d @v gs =10v(-10v) 2.3a -1.7a r dson @v gs =10v(-10v) typ. 126.5m 216m r dson @v gs =4.5v(-4.5v) typ. 130m 227m pin 1 environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t6 : 3000 pcs / tape & reel,13? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c744v8 issued date : 2014.11.03 revised date : page no. : 2/13 MTBA5C10V8 cystek product specification absolute maximum ratings (t c =25c, unless otherwise noted) limits parameter symbol n-channel p-channel unit drain-source breakdown voltage bv dss 100 -100 gate-source voltage v gs 2 20 2 20 v t a =25 c, v gs =10v (-10v) 2.3 -1.7 continuous drain current *2 t a =70 c, v gs =10v (-10v) i dsm 1.8 -1.4 t c =25 c, v gs =10v (-10v) 3.4 -2.6 continuous drain current t c =100 c, v gs =10v (-10v) i d 2.4 -1.8 pulsed drain current * 3 i dm 10 -10 a single device operation 1.5 *2 single device value at dual operation p dsm 1.24 *2 t c =25 c 3.75 total power dissipation t c =100 c p d * 1 1.88 w operating junction and storage te mperature range tj; tstg -55~+175 c thermal data parameter symbol value unit max. thermal resistance, junction-to-ambient, single device operation 84 *2 max. thermal resistance, junction-to-amb ient, single device value at dual operation r th,j-a 101 *2 max. thermal resistance, junction-to-case r th,j-c 40 c/w note : 1 . the power dissipation p d is based on t j(max) =175 c, using junction-to-case thermal resistance, and is more useful in setting the upper di ssipation limit for cases where additional heatsinking is used. 2 . the value of r ja is measured with the device mounted on 1 in 2fr-4 board with 2 oz. copper, in a still air environment with t a =25 c, t 5s . 216 c/w when mounted on a minimum pad of 2 oz. copper. the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150 c. the value in any given application depends on the user?s specific board design. 3. pulse width limited by junction temperature t j(max) =175 c. ratings are based on low duty cycles to keep initial t j =25 c. n-channel electrical characteristics (tc=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 100 - - v gs =0v, i d =250 a v gs(th) 1 - 2.5 v v ds =v gs , i d =250 a i gss - - 100 na v gs =20v, v ds =0v - - 1 v ds =100v, v gs =0v i dss - - 10 a v ds =100v, v gs =0v, tj=70 c - 126.5 155 v gs =10v, i d =2.3a *r ds(on) - 130.0 175 m v gs =5v, i d =2a *g fs - 7 - s v ds =5v, i d =2.3a dynamic ciss - 1221 - coss - 31 - crss - 22 - pf v ds =25v , v gs =0v , f=1mhz
cystech electronics corp. spec. no. : c744v8 issued date : 2014.11.03 revised date : page no. : 3/13 MTBA5C10V8 cystek product specification *t d(on) - 9.2 - *t r - 16.6 - *t d(off) - 37.2 - *t f - 15.6 - ns v ds =50v , i d =1a , v gs =10v , r g =6 *qg - 18.7 - *qgs - 2.7 - *qgd - 3.1 - nc v ds =80v , i d =2.3a , v gs =10v body diode *v sd - 0.78 1.2 v v gs= 0v, i s =2.3a *trr - 18 - ns *qrr - 15.3 - nc i s =2.3a, v gs =0v, di/dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2% p-channel electrical characteristics (tc=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss -100 - - v gs =0, i d =-250 a v gs(th) -1.0 - -2.5 v v ds =v gs , i d =-250 a i gss - - 100 na v gs =20v, v ds =0v - - -1 v ds =-100v, v gs =0v i dss - - -10 a v ds =-10v, v gs =0v, tj=70 c - 216 285 v gs =-10v, i d =-1.5a *r ds(on) - 227 295 m v gs =-5v, i d =-1a *g fs - 5.3 - s v ds =-5v, i d =-1.5a dynamic ciss - 1282 - coss - 58 - crss - 27 - pf v ds =-25v, v gs =0v, f=1mhz *td (on) - 8.4 - *tr - 17.8 - *td (off) - 60.2 - *tf - 18.6 - ns v ds =-50v, i d =-1a, v gs =-10v, r g =6 *qg - 19.1 - *qgs - 3.0 - *qgd - 3.1 - nc v ds =-80v, i d =-1.7a, v gs =-10v body diode *v sd - -0.82 -1.2 v v gs =0v, i s =-2.3a *trr - 16.6 - ns *qrr - 13.4 - nc i s =-2.3a, v gs =0v, di/dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c744v8 issued date : 2014.11.03 revised date : page no. : 4/13 MTBA5C10V8 cystek product specification recommended soldering footprint unit : mm
cystech electronics corp. spec. no. : c744v8 issued date : 2014.11.03 revised date : page no. : 5/13 MTBA5C10V8 cystek product specification typical characteristics : q1( n-channel ) typical output characteristics 0 1 2 3 4 5 6 7 8 9 10 01234 5 brekdown voltage vs ambient temperature 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v 10v, 9v, 8v, 7v, 6v, 5v, 4v v ds , drain-source voltage(v) i d , drain current (a) v gs =3v static drain-source on-state resistance vs drain current 100 1000 10000 0.01 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =3v v gs =2.5v v gs =4.5v v gs =10v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 024681 i dr , reverse drain current(a) v sd , source-drain voltage(v) static drain-source on-state resistance vs gate-source voltage 100 150 200 250 300 350 400 024681 0 0 tj=25c tj=150c v gs =0v drain-source on-state resistance vs junction tempearture 0.4 0.8 1.2 1.6 2 2.4 2.8 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =2.3a r dson @tj=25c : 126.5m v gs =5v, i d =2a r dson @tj=25c : 130m typ. v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =2.3a
cystech electronics corp. spec. no. : c744v8 issued date : 2014.11.03 revised date : page no. : 6/13 MTBA5C10V8 cystek product specification typical characteristics(cont.) : q1( n-channel) capacitance vs drain-to-source voltage 10 100 1000 10000 0.1 1 10 100 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 i d , drain current(a) g fs , forward transfer admittance(s) v ds =5v pulsed ta=25c gate charge characteristics 0 2 4 6 8 10 0 5 10 15 20 qg, total gate charge(nc) v gs , gate-source voltage(v) i d =2.3a v ds =80v maximum safe operating area 0.001 0.01 0.1 1 10 100 0.1 1 10 100 1000 v ds , drain-source voltage(v) i d , drain current(a) t a =25c, tj=150c v gs =10v, ja =84c/w single pulse dc 100ms r dson limite 100 s 10ms 1ms 1s maximum drain current vs junction temperature 0 0.5 1 1.5 2 2.5 3 25 50 75 100 125 150 175 tj, junction temperature(c) i d , maximum drain current(a) t a =25c v gs =10v r ja =84c/w
cystech electronics corp. spec. no. : c744v8 issued date : 2014.11.03 revised date : page no. : 7/13 MTBA5C10V8 cystek product specification typical characteristics(cont.) : q1( n-channel) typical transfer characteristics 0 1 2 3 4 5 6 7 8 9 10 0123456 v gs , gate-source voltage(v) i d , drain current(a) v ds =5v single pulse power rating, junction to ambient (note on page 2) 1 10 100 0.001 0.01 0.1 1 10 100 1000 pulse width(s) power (w) t j(max) =150c t a =25c ja =84c/w transient thermal response curves 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) r(t), normalized transient thermal resistance single pulse 0.01 0.02 0.05 0. 1 0. 2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t1/t2 3.t jm -t a =p dm *r ja (t) 4.r ja =84c/w maximum drain current vs case temperature 0 0.5 1 1.5 2 2.5 3 3.5 4 25 50 75 100 125 150 175 200 tc, case temperature(c) i d , maximum drain current(a) v gs =5v r jc =40c/w tj(max)=175c
cystech electronics corp. spec. no. : c744v8 issued date : 2014.11.03 revised date : page no. : 8/13 MTBA5C10V8 cystek product specification typical characteristics : q2( p-channel) typical output characteristics 0 2 4 6 8 10 01234 5 brekdown voltage vs ambient temperature 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) -bv dss , normalized drain-source breakdown voltage -i d =250 a, v gs =0v -v ds , drain-source voltage(v) -i d , drain current (a) 10v 9v 8v 7v 6v 5v 4v -v gs =3v static drain-source on-state resistance vs drain current 100 1000 10000 0.01 0.1 1 10 100 -i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) -v gs =3v -v gs =2.5v -v gs =4.5v -v gs =10v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 02468 -i dr , reverse drain current(a) -v sd , source-drain voltage(v) 10 tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 200 250 300 350 400 450 500 550 600 024681 0 drain-source on-state resistance vs junction tempearture 0.4 0.8 1.2 1.6 2 2.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =-10v, i d =-1.5a r dson @tj=25c : 216m typ. v gs =-5v, i d =-1a r dson @tj=25c : 227m typ. -v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) -i d =1.5a ?
cystech electronics corp. spec. no. : c744v8 issued date : 2014.11.03 revised date : page no. : 9/13 MTBA5C10V8 cystek product specification typical characteristics(cont.) : q2(p-channel) capacitance vs drain-to-source voltage 10 100 1000 10000 0.1 1 10 100 -v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.4 0.6 0.8 1 1.2 1.4 1.6 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) -v gs(th) , normalized threshold voltage i d =-250 a forward transfer admittance vs drain current 0.01 0.1 1 10 0.001 0.01 0.1 1 10 -i d , drain current(a) g fs , forward transfer admittance(s) v ds =-5v pulsed ta=25c gate charge characteristics 0 2 4 6 8 10 0 4 8 12 16 20 24 qg, total gate charge(nc) -v gs , gate-source voltage(v) i d =-1.7a v ds =-80v maximum safe operating area 0.001 0.01 0.1 1 10 100 0.1 1 10 100 1000 -v ds , drain-source voltage(v) -i d , drain current(a) t a =25c, tj=150c v gs =-10v, ja =84c/w single pulse dc r dson limite 100 s 1ms 10ms 100ms 1s maximum drain current vs junction temperature 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 25 50 75 100 125 150 175 tj, junction temperature(c) -i d , maximum drain current(a) t a =25c v gs =-10v r ja =84c/w
cystech electronics corp. spec. no. : c744v8 issued date : 2014.11.03 revised date : page no. : 10/13 MTBA5C10V8 cystek product specification typical characteristics(cont.) : q2(p-channel) typical transfer characteristics 0 1 2 3 4 5 6 7 8 9 10 0123456 -v gs , gate-source voltage(v) -i d , drain current(a) v ds =-5v single pulse power rating, junction to ambient (note on page 2) 1 10 100 0.001 0.01 0.1 1 10 100 1000 pulse width(s) power (w) t j(max) =150c t a =25c ja =84c/w transient thermal response curves 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) r(t), normalized transient thermal resistance single pulse 0.01 0.02 0.05 0. 1 0. 2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t1/t2 3.t jm -t a =p dm *r ja (t) 4.r ja =84c/w maximum drain current vs case temperature 0 0.5 1 1.5 2 2.5 3 25 50 75 100 125 150 175 200 t c , case temperature(c) -i d , maximum drain current(a) v gs =-5v r jc =40c/w tj(max)=175c
cystech electronics corp. spec. no. : c744v8 issued date : 2014.11.03 revised date : page no. : 11/13 MTBA5C10V8 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c744v8 issued date : 2014.11.03 revised date : page no. : 12/13 MTBA5C10V8 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
spec. no. : c744v8 issued date : 2014.11.03 revised date : page no. : 13/13 cystech electronics corp. MTBA5C10V8 cystek product specification dfn3 3 dimension millimeters inches millimeters inches dim min. max. min. max. dim min. max. min. max. a 0.650 0.850 0.026 0.033 b 0.200 0.400 0.008 0.016 a1 0.152 ref 0.006 ref e 0.550 0.750 0.022 0.030 a2 0.000 0.050 0.000 0.002 l 0.300 0.500 0.012 0.020 d 2.900 3.100 0.114 0.122 l1 0.180 0.480 0.007 0.019 d1 0.935 1.135 0.037 0.045 l2 0.000 0.100 0.000 0.004 d2 0.280 0.480 0.011 0.019 l3 0.000 0.100 0.000 0.004 e 2.900 3.100 0.114 0.122 h 0.315 0.515 0.012 0.020 e1 3.150 3.450 0.124 0.136 9 13 9 13 e2 1.535 1.935 0.060 0.076 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance . marking: 8-lead dfn3 3 plastic package cystek package code: v8 date code s1 g1 s2 g2 d1 d1 d2 d2 ba5 c10

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